`timescale 1ns/10ps

module top_tb;
reg clk;


// Clock generation
initial begin
    clk = 0;
    forever #10 clk = ~clk; // 10ns clock period
end


top top_inst (
    .sys_clk(clk),
    .key(0),
    .sw(4'b1000)
);
wire [7:0] MAR_reg;
assign MAR_reg = top_inst.mar_data;
wire [15:0] MBR_reg;
assign MBR_reg = top_inst.mbr_data;
wire [7:0] PC_reg;
assign PC_reg = top_inst.pc_data;
wire [15:0] IR_reg;
assign IR_reg = top_inst.ir_data;
wire [15:0] ACC_reg;
assign ACC_reg = top_inst.acc_data;
wire [15:0] BR_reg;
assign BR_reg = top_inst.br_data;
wire [15:0] MR_reg;
assign MR_reg = top_inst.mr_data;
wire [15:0] AX_reg;
assign AX_reg = top_inst.ax_data;
wire [15:0] BX_reg;
assign BX_reg = top_inst.bx_data;
wire [15:0] CX_reg;
assign CX_reg = top_inst.cx_data;
wire [15:0] DX_reg;
assign DX_reg = top_inst.dx_data;
wire [15:0] SP_reg;
assign SP_reg = top_inst.sp_data;

    
endmodule
